Circuit Design Engineer, Physical Design Engineer
May 12, 2017 Silego Technology,   Santa Clara, CA

 

2017 CASPA/SEMI High Tech Job Fair

 

Silicon Valley                                                        

May 13, 2017 (Sat) 10:00 AM - 4:00 PM                         

Crowne Plaza San Jose-Silicon Valley,

777 Bellew Dr, Milpitas, CA 95035 

  

                                                             About Silego Technology

 

Silego Technology, Inc. is a fabless semiconductor company headquartered in Santa Clara, California with operations in Taiwan, and additional design/technology centers in China, Korea and Ukraine.

Silego designs and sells highly configurable power, logic, and timing mixed signal IC products referred to as CMICs (Configurable Mixed-signal IC Products). The CMIC products integrate medium precision analog components, discrete digital logic, and passive components into highly configurable small, easy to use, low cost ICs. CMIC products provide customers the benefits of reduced system parts count, lower power consumption, less board space and reduced BOM costs. CMICs provide the flexibility of an FPGA and have similar pricing to ASICs without nonrecurring engineering costs, and long design cycles. Silego’s goal is to allow electronics manufacturers to integrate 20 components in 20 minutes for $0.20.

Silego’s customers include many leading OEMs that manufacture and sell Personal Computers systems, data communication equipment, and consumer electronic devices. Silego was recognized in 2010 by Deloitte Technology Fast 50 Rising Star ranking as one of the fastest growing technology companies in Silicon Valley.

 

 

New Job Positions for Silego

 

Job search URL: http://www.silego.com/companymain/careers.html

 

 


Circuit Design Engineer (All levels) (Santa Clara)

 

We are looking for experienced analog/mixed-signal design engineer for developing complex configurable power, logic, and timing mixed signal IC products referred to as CMICs (Configurable Mixed-signal IC Products). The individual will take a role in defining and implementing the overall system architecture, designing transistor-level analog circuit blocks, simulating sub-system performance, creating and using behavioral models of the entire IC, overseeing chip integration, doing and/or supervising physical layout, verifying circuit and chip-level operation and performance, and assisting with tape-out related activities. The qualified designers also have good knowledge in semiconductor device physics and process technologies.

 

Responsibilities:

  • Design of Analog and Mixed-Signal circuits, meeting their architectural requirements and specifications.
  • Contribute to the architectural definition of the design, and also to chip integration
  • Perform the necessary calculations, design and verification simulations to ensure building blocks meet specifications, at the schematic level and after post layout extraction.
  • Work closely with Layout Designers to ensure the layout is completed properly, using all known methods.
  • Document for assigned blocks, test and characterization report, and hold preliminary/final design reviews.
  • Actively participate in the chip bring up, evaluation and characterization, with emphasis on owned blocks
  • Address questions and issues related to his/her blocks raised by cross-functional personnel, such as Product, Characterization, Test, or Application Engineers.

 

 Requirements:

  • BSEE required, MSEE preferred, with minimum 5 years of direct working experience.
  • Knowledge of languages: Matlab, VerilogA, Verilog-D
  • Ability to oversee circuit layout for critical blocks
  • Fluent in design tools: Cadence (icfb, virtuoso), Calibre, Assura, Verilog.
  • Knowledge and experience in analog/mixed signal circuits: PLL, bandgap reference, OpAmp, regulator, combinational logic, dividers. RTL & logic design flow is a plus.

 

 

Physical Design Engineer (All levels) (Santa Clara)

 

We are looking for experienced analog/mixed-signal physical design engineer for mixed signal IC products. The individual can work closely with designers, effectively take instructions, and assisting with tape-out related activities. Having good knowledge in semiconductor device physics and process technologies is a plus.

 

Responsibilities:

  • Efficiently understand and apply Physical Design Rule for given technology in the assignments.
  • Work closely with designers to ensure the layout is completed properly, using all known methods.
  • Chip and/or block level floor planning, pin and/or bus planning, Power planning.

 

 Requirements:

  • Minimum 5 years of direct working experience.
  • Fluent in physical design tools: Cadence Calibre, Assura
  • Fluent in Physical Verification (DRC/LVS/ERC/ANT) with digital and mixed-signal designs