Principal Physical Design/Timing/VLSI Technology Engineer, etc.
Nov 14, 2016 ZTE,   USA

all the below positions are based in the U.S. 


1)        Principal Physical Design/Timing/VLSI Technology Engineer 

JOB Responsibilities: 
- Advanced process technology node engagement 
- Design timing sign off for complex chips in advanced process nodes (16nm/14nm, 10nm, 7nm) 
- STA corners and margins definition, sign-off guidelines 
- New timing methodology (STA/AOCV/SSTA) 
- Timing corner coverages 
- Post-silicon debug and Methodology 

Masters in Electrical or Computer Engineering and at least 5 years of experience in the following areas (at least 3 items): 

- Semiconductor device modeling and MOL/BEOL modeling 
- Process/design reliability and aging 
- Liberty library modeling and characterization 
- PD implementation: ICC/ICC2, EDI/Innovus, Olympus, StarRC-XT, Calibre, Tweaker 
- RTL to GDS design flow in 16nm Finfet or below (16/14/10/7nm) 
- AOCV timing methodology, LVF modeling, Design/IP margin analysis, Monte Carlo analysis, Linear programing and optimization 
- Hand on experience with STA timing convergence, Timing closure and signoff , ECO flows, SOC timing sign off tapeouts 
- Static timing analysis tools, delay calculators, fast spice simulators. 
- Circuit spice simulation and verification 
- Bilingual in English and Chinese is required 


2)  Principal Package Design engineer 

JOB Responsibilities: 
- Advanced package technology node engagement (Cowos/3D) 
- Bump pattern definition, pinout, package substrate stack-up and routing strategy definition 
- Perform package modeling 
- Guide package design or ATE design & yield of 16nm FinFET or below (16/14/10/7nm) for high-speed interface such as SERDES which at least 25Gbps and DDR3/4 
- Develop scripts for pre- and post-processing automation 

Masters in Electrical or Computer Engineering and at least 5 years of experience in the following areas (at least 3 items): 
-        Digital package design focused primarily on signal/power integrity 
-        DDR3/4 and LPDDR3/4 package design and analysis 
-        High-speed serial I/O (at least 25Gbps) package design and analysis 
-        One or more commercial SI tools such as Ansys tools, PowerSI and/or Sentinel-PSI 
-        Electromagnetic theory and its application to high-speed transmission lines 
-        Sigrity, Agilent, and MATLAB tools desirable 
-        Ansys HFSS or a similar 3D electromagnetic field solver 
-        Skill and experience of ATE & Yield is needed 
-      Bilingual in English and Chinese is required 


3)  Principal RF engineer 
一.职位描述 
1.负责或参与射频芯片的架构设计、接口设计及链路仿真。针对产品的指标要求,提出相应的设计方案,并能对方案作进一步的评估分析; 
2.依据设计的架构方案进行链路预算分析,并能将指标分解到各个功能单元; 
3.参与射频芯片制程工艺的选择评估和分析,对射频芯片的性能、面积、功耗、成本进行分析评估并给出建设性意见; 
4.按照射频芯片的开发流程,协助制订射频芯片整体以及各功能单元的开发计划。并能够对各功能单元的开发过程进行质量把控,以及对各功能单元的开发提供技术指导。在整个开发流程中,负责或参与关键问题的解决和技术攻关; 
5.负责或参与射频芯片的版图布局,并能够指导、支持版图设计工作; 
6.参与射频芯片的封装设计; 
7.参与射频芯片的测试方案设计,对芯片测试过程中出现的问题作分析判断,并及时总结对设计进行改进。 

二.职位要求 
1.电子工程、微电子、通信工程及微波等相关专业,硕士及以上学历。10年及以上的射频芯片设计开发经验; 
2.深入理解射频/模拟/混合信号电路的设计原理、设计方法/技巧。对射频链路涉及的带宽、增益、相位噪声、杂散、线性度、隔离度、噪声系数等指标有深入的理解,并掌握相应的电路设计方法、技巧和注意事项; 
3.有射频芯片的架构设计、链路方案设计以及链路仿真经验。能进行复杂的射频链路预算分析,并将指标分解到各功能单元; 
4.熟悉射频/模拟芯片的制程工艺,熟悉目前业界主流制程工艺的性能、面积、功耗特征; 
5.有作为SE至少一次以上复杂的射频芯片系统设计及流片经验,例如:TRX、ADC/DAC、mixer、LNA、VGA/AGC等等。 
6.熟练掌握射频电路设计的EDA工具(Spectre/SpectreRF、ADS等); 
7.对射频芯片的版图设计有深入的了解,熟悉相关的EDA工具; 
8.熟悉射频芯片的封装设计; 
9.熟悉射频系统及射频电路调试方法,熟悉各种RF测试仪器的操作; 
10.熟悉无线通信原理,熟悉无线收发信机产品。了解3G/4G NodeB RRu产品者优先; 
11.具有良好的沟通及组织能力,具有良好的抗压能力以及团队协作精神。