Job Location: San Jose, California
Hiring Manager: Director, Memory Design Program
• Hands-on design of SRAM memory circuits & compiler timing/power characterization, netlist/ layout tiling, IR/ EM flow.
• Supervision of layout, compiler coding. Supervision and interpretation of testing results.
• SRAM Compiler verification/QC.
• The individual would primarily be a technical contributor, be part of a design R&D team and frequent interaction with Headquarters in Hsinchu, Taiwan.
• Individual contributor, need to be hands-on for all the compiler related work, not limited to circuit design only.
· BS, MS or PhD degree in semiconductor related fields.
• 5+ years SRAM or other memories design experience.
• SRAM compiler experience preferred.
• High speed and low power memory design experience preferred.
• Experienced in Cadence & Synopsys circuit design environment preferred.
• Experienced in advanced technology circuit design & layout preferred (20nm/16nm/10nm/7nm).
• Must have good team work attitude.
TSMC Technology Inc. is an Equal Opportunity Employer.
For submitting the resume, please have them send it to email@example.com