Position Title: Principal Engineer
Dept Name: MSD-HSIO Majority of Work Performed (City,State): Portland, OR
Faraday Technology is looking for talented & experienced analog and mixed-signal design engineers to join us in developing the most advanced high-speed IPs in our newly established design center at Portland, OR. In this position you’ll be one of the leaders in developing the state of the art multi-GHz high speed IOs, ADC/DAC, & clock generation IPs. From architecture & design methodology definition, project execution, post-silicon validation, and support field application engineers. The qualified candidate must have a proven track record of designing complex ICs in most advanced CMOS process, deep knowledge in IP design methodology/tool flows and IP integration at both SoC and system level. And has successfully placed design into volume production. You’ll also be collaborating with international teammates in design execution, IPs porting, and customer evaluation/ acquisition & support.
· MSEE or PHD with minimum of 12+ years experience in deep sub-micron analog/mixed signal circuit design
· High speed and analog circuit design experience including one or more of the following: PLLs, DLLs, ADC/DAC, LDO, high-speed custom transceiver, Serdes, clock and data recovery, DDRx/LPDDRx driver or receiver.
· Knowledge & hands-on experience with one or more of the following IO protocols: PCIe, SATA, USB, SGMII, Interlaken, 10G Base–KR, CEI, FC, XAUI, XPON, DDR3/4, LPDDR3/4, Intel PIPE 3.0 and above.
· A track record in delivering high volume commercial products from architecture definition to post-silicon product qualification, & working knowledge in industry best practices
· Previous experience in TSMC/UMC’s 40nm process or more advanced node, PI/SI & channel analysis, and Hard IP’s SoC/system integration & validation flow is a strong plus.
· Past experience in supporting deal acquisition and external customer engagement is a must.
· Strong fundamental in circuit theory, design and layout
· Knowledge in digital signal processing, control theory, system behavior modeling with matlab/IBIS-AMI or Verilog/Verilog-A, and IO’s training algorithm is a strong plus
· Creative design and problem solving ability delivering the highest level result across power, performance and area
· Experience in Cadence, HSPICE design flow, static timing analysis, and analog-mixed signal behavior modeling and verification
· Strong communication and presentation skills. Ability to work independently with local and international teams under different time zone and language background.
Ability to work across all functional levels. Highly disciplined and self-motivated. Able to support occasional domestic or international travel per business requirement.
Contact person: Andrew Chao