Staff Engineer (digital and mixed-signal)
May 21, 2019 Faraday Technology Corporation,   Portland, OR

Position Title: Staff Engineer                                        

Supervisor: Andrew Chao                   

Dept Name: MSD-HSIO                           Majority of Work Performed(City,State): Portland, OR



Faraday Technology is looking for talented & experienced digital and mixed-signal design engineers to join us in developing the most advanced high-speed IPs in our newly established design center at Portland, OR. In this position you’ll be one of the leaders in developing the state of the art multi-GHz high speed IOs, ADC/DAC, & clock generation IPs. From architecture & design methodology definition, project execution, post-silicon validation, and support field application engineers. The qualified candidate must have a proven track record of designing complex ICs in most advanced CMOS process, deep knowledge in IP design methodology/tool flows and IP integration at both SoC and system level. And has successfully placed design into volume production. You’ll also be collaborating with international teammates in design execution, IPs porting, and customer evaluation/ acquisition & support.     






·      MSEE or PHD with minimum of 6+ years experience in deep sub-micron mixed signal design

·      High speed digital PMA/PCS design experience including one or more of the following PHY architecture: Serdes, DDRx, LPDDRx or RF. 

·      Knowledge & hands-on experience with one or more of the following IO protocols: PCIe, SATA, USB, SGMII, CEI, FC, Interlaken, XAUI, XPON, DDR3/4, LPDDR3/4, Intel PIPE 3.0 or above. 

·      Knowledge and hands-on experience on digital physical media attachment (DPMA) from architecture definition, RTL coding, logic & mixed signal verification, IP collateral generation, to post-silicon validation at both component & system level. 

·      A track record in delivering high volume commercial products from architecture definition to post-silicon product qualification, & working knowledge in industry best practices  

·      Previous experience in TSMC/UMC’s 40nm process or more advanced node and Hard IP’s SoC/system integration & validation flow is a strong plus.

·      Past experience in supporting deal acquisition and external customer engagement is a must.



·      Strong fundamental in digital, mixed signal and ASIC design & verification. 

·      Strong coding skill in Perl, C, Verilog, System Verilog. Past experience with Python, Verilog-AMS, Verilog-A is a strong plus. 

·      Experience with tools/flows such as VCS, Design/RTL compiler, Formality, CDC, Discovery-AMS, LINT, UVM/OVM/VMM, B-scan, UPF & Scan/BIST , DFT, FPGA flow.

·      Past experience with one of more of the following buses: I2C, AMBA AXI/APB/AHB, PCS, TAP/JTAG, Boundary scan, Memory-mapped-IO,   

·      Knowledge in digital signal processing, control theory, system behavior modeling, power management & power-up sequence, clocking and data pipeline/latency, and IO’s training algorithm is a strong plus

·      Knowledge of Physical implementation flows, such as Synthesis, floor-planning, design constrain, CTS, ICC, design/timing convergence, and reliability flows. 

·      Creative design and problem solving ability delivering the highest level result across power, performance and area 

·      Strong communication and presentation skills. Ability to work independently with local and international teams under different time zone and language background.

·      Ability to work across all functional levels. Highly disciplined and self-motivated. Able to support occasional domestic or international travel per business requirement.