Senior Design Verification Engineer
Jul 10, 2019 瑞昱半導體 Realtek Semiconductor Corp.,   Hsinchu , Taiwan

Responsibilities:
1. Responsibility for test plans, test bench documentation and implementation.
2. Use System Verilog language, SVA and UVM methodology for block and top level verification.
3. Apply formal property checking/formal verification methodologies
4. Understanding of the fundamentals of computer architecture

Requirements:
0. 5+ years working experience.
1. MS Degree or above in Electrical, Electronics or Computer Engineering.
2. Familiar with System Verilog, SVA, Perl, CRV, VMM/UVM Methodology.
3. Familiar with EDA Tools such as Formal Verification Tool (Cadence Jasper, Synopsys Magellan).
4. Good analytical problems solving skills.
5. Good C/C++ Programming skills.
6. Good verbal and written communication skills.
7. Self-motivated and possess team working skills.

Corporate Website: https://www.realtek.com/en/
For submitting the resume, please send it to: tiff_liang@itri.org.tw;a989102@itri.org.tw;serena_lee@itri.org.tw