Senior Design Verification Engineer
Jul 10, 2019 瑞昱半導體 Realtek Semiconductor Corp.,   Hsinchu , Taiwan

1. Responsibility for test plans, test bench documentation and implementation.
2. Use System Verilog language, SVA and UVM methodology for block and top level verification.
3. Apply formal property checking/formal verification methodologies
4. Understanding of the fundamentals of computer architecture

0. 5+ years working experience.
1. MS Degree or above in Electrical, Electronics or Computer Engineering.
2. Familiar with System Verilog, SVA, Perl, CRV, VMM/UVM Methodology.
3. Familiar with EDA Tools such as Formal Verification Tool (Cadence Jasper, Synopsys Magellan).
4. Good analytical problems solving skills.
5. Good C/C++ Programming skills.
6. Good verbal and written communication skills.
7. Self-motivated and possess team working skills.

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