Principal Design Engineer (数字前端设计)
Aug 2, 2019 Cadence ,   Shanghai/Beijing, China

Position Description:  

Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.  


Specific duties include:  

Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow  

Proficiency in logic design, simulation, synthesis, STA and testing  

Proficiency in Verilog and its simulation environment  

Good knowledge of IC design  

At least five years’ experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.  


Position Requirements:  

Essential Qualifications: Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.  

Essential that the individual demonstrates strong communication, verbal and written.  

Requires good communication skills in English.  


please submit your application to job_china@cadence.com