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Broadcom's Design Access group in Central Engineering is looking for an energetic and self-driven professional to join our team to help with IP and product design at the 5nm and 3nm nodes. Our mission is to define and deliver the process technology roadmap and platform for product design and provide Broadcom’s internal design communities with insight into design and process-technology interactions especially during co-development at advanced nodes.
The candidate will have the opportunity to participate in technology platform definition, PPA assessment and benchmarking for the most advanced technology nodes offered from various foundries, with current focus on 5nm and 3nm nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers in each product line. Duties will also include running SPICE simulations, silicon-to-simulation gap analysis, managing design collateral distribution and negotiating schedules, performance/yield/reliability trade-off analysis, development of new device concepts, and managing the foundry partner to meet IP and product schedules.
Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on-time, and possess excellent data analysis & foundry management skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. If hired, the candidate is expected to be physically located in Broadcom’s Irvine facility in California.
Candidate will support IP and chip teams with design collateral access needs and provide process technology configuration selection, device targeting/positioning, as well as design flow recommendations/guidelines/solutions mainly based on PPA, reliability qualification and tape-out schedule. Industry experience in deep sub-micron CMOS process technology and device physics/modeling is required, with hands-on experience in HKMG FinFET process technology at 7nm and 5nm nodes desired. Experience with foundry management, support of CAD tool and VLSI circuit design teams, familiarity with EUV lithography, will be a plus. Candidate will also work with internal CAD/Modeling/TF teams as well as foundry partner for BRCM custom device development, qualification and deployment. The candidate is expected to engage in collaborative new project development on team as well as single person projects.
The minimum engineering experience required is a MS degree in EE/CS with 10+ years of industry experience, or Ph.D. degree in EE with 7+ years of industry experience, with recent work in 7nm or more advanced FINFET nodes. Process technologists with integration/module /device backgrounds with majors in materials science or chemical engineering, but with some exposure to basic electrical engineering & design/simulation concepts, are also welcome.
Strong deep sub-micron CMOS device physics background
In-depth CMOS process, process integration, and manufacturing knowledge
In-depth knowledge of IC circuit design & design flow
Proficient in running tools for data analysis and correlation studies
Experience with creating test structures and performing DRC & eJV.
Experience with CMOS digital circuit SPICE simulation and statistical simulation like Monte Carlo analysis.
Familiarity with standard cell library characterization and CAD tools
Familiarity with IC chip design flow, timing and power sign-off characterization
Strong analytical skills and extremely detail oriented.
Strong communication skills.
Strong multitasking skills.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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