• Full Time
  • Anywhere
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Avance Semi Inc


Job Description:
We are developing high-speed data communication SOC chips, including modulation, demodulation, channel equalization and forward error correction. The work includes two stages, FPGA prototype development and ASIC chip development. Your responsibilities would include RTL coding, design and design verification, as well as synthesis, static timing analysis, emulation and prototype bring-up support. You will work very closely with the algorithm team, architecture team, as well as ASIC back-end development team.

Roles and Responsibilities:
o Understand the algorithm to complete the fixed-point design;
o Develop the FPGA design methodology;
o Synthesis, static timing analysis, equivalence checking;
o FPGA implementation, prototype bring up and emulation.

The successful candidate will possess the following combination of education and experience:
o MTech/BTech in EE/EC domain or equivalent;
o 3+years of experience in a design engineering role focusing on FPGA coding, simulation, synthesis, place androute, debug and timing analysis;
o Proficiency in Verilog language, RTL and behavioral coding;
o Knowledge of Signal processing concepts and fixed-point signal processing;
o Experience on Xilinx FPGA with the Vivado platform;
o Ability to analyze system-level performance and bottlenecks.

Bonus experience and skills:
o C programming used in conjunction with chip design and verification highly desired;
o Chip/ASIC design or verification experience;
o FPGA simulation experience using Mentor Graphics Modelsim;
o Hands on experience with PCIe (Master or slave), Aurora, High-speed transceiver (GTY), I2C, SPI, etc.