SoC Design Engineer / Manager

What can eTopus do for you?

  • Potential for upward mobility in a fast-moving Silicon Valley startup.
  • Opportunity to work with the like-minded talent to solve challenging problems.
  • Becoming part of the creator of ultra-high speed interconnect technology to enable the next generation of Cloud Data Centers.

What can you do for eTopus?

Handles all aspects of digital design in SoC level for networking devices, this includes SoC micro-architecture definition, system integration, clock domain specification, area, and power estimation, DFT architecture definition.

Specific job description:

  • Interface with Marketing, potential customers and perform SoC micro-architecture definition.
  • Define Intellectual Property Specification, Vendor Selection, System Integration.
  • Responsible for chip-level integration which includes internal and external IPs, microprocessors.
  • Drive system level functional verification.
  • Drive SoC timing closure, drive DFT solution.
  • Drive signal integrity and power integrity flow.
  • Drive total SoC PPA optimization.

Required skills and experience

  • Hands-on experience in Verilog, simulation & synthesis tools, Tcl, Perl, Python, and Matlab scripting.
  • Hands-on experience with lab equipment.
  • Experience with 10G+ networking or communication development a plus.
  • Advanced CMOS technologies such as 40nm, 28nm and below.


  • BS/MS/PhD in EE and Computer Engineering with multiple Tape-out experience for <40nm process.

Working location: Hong Kong office / Headquarters & Innovation Center


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