The memory controller is the core technology of the SOC design. It provides the data that all functional modules need to work. We are seeking excellent and potential ASIC design engineers to implement the world’s leading memory controller IPs.

As a key member of system and memory controller team, you will be responsible for the implementation the SOC system bus performance and memory controller design for the latest LPDDR5/4/4x DDR4/DDR3 SDRAM.  Detailed responsibilities may include, but not be limited to


  • Documentation of design specifications.
  • Use design specification to do RTL digital design and verification.
  • Cooperate with backend team to do synthesis, and timing check, power analyses.

Job Qualifications:

  • BS/MS/PHD in Electrical Engineering
  • Fluent in RTL design with Verilog/System Verilog, synthesis and timing closure.
  • Good problem solving and communication skills

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