- MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
- Experience with Verilog and system Verilog
- Experience with VCS, and UVM design verification tools.
- Experience with pre-layout simulation and post-layout simulation
- Understanding of the design flow. Ability to work with the backend team
- Familiarity with AMBA APB AXI Protocol
- Familiarity with RISC/Arm or other core architectures
- Ability to create innovative architecture and solutions to customer requirements
- Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.
Experience in one or more of the following areas considered a strong plus:
- FPGA/ASIC design of image processing systems
- Working knowledge of SoC architecture such as CPU, GPU or accelerators
- Familiarity with: UVM, place-and-route, STA, EM/IR/Power
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