Responsible for all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, and final DRC/LVS.

Job Qualifications:

  • BSEE, MSEE or higher.
  • At least 5 years’ experience of large ASIC backend designs.
  • Experience with Synopsys and/or Cadence and/or Mentor Graphics design tools.
  • Familiar with 28nm, 16nm and/or 7nm VLSI backend designs.
  • Good communication skills, team spirit.

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