- Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
- Contribute significantly to verification infrastructure development
- Development of System Verilog/UVM based on test plan from functional requirements
- Maintain regression list and run regression tests to make sure the design works correctly.
- Master degree desired, Bachelor’s degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field.
- Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs
- Should have worked on developing/implementing test plans at the chip-level for complex ASICs. • Fluent in System Verilog and scripting languages such as Python or Perl.
- Must have intimate knowledge of UVM methodology. • Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
- Knowledgeable about assertions and functional coverage
- Experience with code coverage, formal verification tools; familiarity with evolving verification
- Very good communication skills and ability and desire to work in a geographically diverse team environment
- Dental insurance
- Health insurance
- Paid time off
- Vision insurance
- Freeonsite lunch
To apply for this job email your details to firstname.lastname@example.org