Location: Santa Clara, CA



We are currently looking for interns with solid Computer Engineering, Computer Science and ML backgrounds who would be interested in exploring the applications of ML, statistical learning and optimization methodologies in the estimation of modern hardware power consumption.



Responsibilities and opportunities to learn:

  • Work with the machine learning branch of our CPU design team.
  • Apply machine learning to the power estimation of HW/CPU.
  • Help explore and develop applications of ML and statistical learning in various aspects of HW design process – e.g., design space exploration, verification and instruction set generation, chip physical layout, etc.
  • Collaborate with fellow machine learning research engineers on a regular basis on general ML topics such as GNNs, etc., with potential application in system and HW design pipelines.



Prefer candidates with multiples of the following qualifications:

  • Knowledge of Deep Reinforcement Learning, Statistical Learning including DNN, GNN and sequence processing, as well as optimization and search techniques.
  • Familiarity with ML architectural designs and ML software environment platforms such as PyTorch or Tensorflow.
  • Knowledge of logic design and power estimation techniques.
  • Agility in learning and working with multiple tools, including research and commercial tools.
  • Well organized, detail-oriented team player.
  • Good verbal and written communication skills.
  • Ph.D or M.S. candidate in CS / ECE or closely related majors.


To apply for this job please visit phf.tbe.taleo.net.