Job Title: Senior Staff Engineer, CPU Design Verification (Contractor)
Location: Santa Clara, CA or Austin, TX
To Apply: please send your resume to firstname.lastname@example.org
Position is for CPU Design Verification Engineers at various levels for a family of high-end 64-bit super scalar RISC-V based micro-processors.
Responsibilities (depends on the detailed assignment, the candidate may carry out portions of the responsibilities below):
• Responsible for the verification of a CPU sub-block (Instruction Fetch Unit, Out-of-Order Unit, Floating-Point Unit, Vector Unit, Load Store Unit, Level 2 Cache Unit, MP cache coherency) at the unit-level testbench and/or at the core-level testbench.
• Draft and review the test scheme and test plan.
• Develop unit-level testbench and/or core-level testbench verification components.
• Work with a team of RTL designers and DV engineers in development of test cases at the unit-level and/or core-level (developing test-cases using an in-house random test generator).
• Develop assertions, checkers, functional coverage according to the testplan.
• Run nightly regressions, triage & debug failures.
• 4-10 years of experience in verification of CPU designs.
• Strong experience/knowledge in UVM and System Verilog, and assertion-based verification.
• Experience in programming/scripting languages, such as C/C++, python, perl.
• Must be a highly organized, detail-oriented self-starter, who works well independently, as well as in a team environment.
• Good verbal and written communication skills.
• Master’s degree preferred.
• Preference for candidates who have previous experience in core-level CPU verification and assembly programming in RISC-V, ARM, or X86.