• IP integration and verification for the SOC
  • Perform logic design and simulation
  • Perform SOC design check like lint, CDC and etc according to the SOC design flow
  • Participate the SOC architecture and microarchitecture design and SOC performance simulation
  • Cooperate with analog team and backend team for the interface check, timing check, power analysis and chip floorplan guide
  • Documentation of SOC design specifications
  • Assist with debug and bring-up of the SOC
  • Communicate and support software, hardware and other related teams

Job Qualifications:

  • BS/MS/PHD in Electrical Engineering or related STEM.
  • Solid experience in RTL design with Verilog/System Verilog.
  • Good problem solving and communication skills.
  • Familiarity with general bus architecture and protocols like AMBA, I2C, UART, JTAG etc.
  • Familiarity with ARM, RISC or other core CPU architecture.
  • Familiarity with all front-end tools including VCS, lint, CDC, Verdi, synthesis, perl  et
  • Familiarity with the DFT
  • ARM SOC design experience preferred

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