Jobfair2022 TSMC

1:15-2:25 pm Hiring company introduction Session
2:30-4:5 0pm Individual Company Interactive Session
3:50-4:50 pm Career Growth Seminar for all attendees

* Zoom links will be provided before the event for registered attendees.
* Please register at
* Individual Company Interactive Session can be extended to 5:30 pm if the company wants

Get to know TSMC

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About TSMC

Taiwan Semiconductor Manufacturing Company Limited engages in the computer aided design, manufacture, packaging, testing, sale, and marketing of integrated circuits and other semiconductor devices. The company is also involved in the research, development, design, manufacture, and sale of solid state lighting devices and related applications products and systems; and renewable energy and efficiency related technologies and products, as well as manufactures masks. In addition, it provides customer and technical support services; and sells and markets solar related products. Taiwan Semiconductor Manufacturing Company Limited operates in Taiwan, the United States, Asia, and internationally. The company was founded in 1987 and is headquartered in Hsinchu, Taiwan.
TSMC North America is the sales and service organization for the world’s largest semiconductor foundry with headquarters based in Taiwan. TSMC NA works with customers in the technology business that manufactures and sells products that run on our chips and cutting edge technology.

Job Type Req Number Job Title Location Notes URL Posting Application Email
Full time 2200000D Technical Manager/ Account Manager San Jose • Bachelors or master’s degree of Science or Engineering from a top accredited university
• At least 7 years of combined experience in Technical Sales, Marketing, Business Development, or Foundry Management in semiconductor industry is preferred
• Good knowledge of semiconductor technology, design, process, and operations including test and product engineering
Full time 210000DF Project/ Program Manager San Jose BSEE required
7+ years experience in Special Technogoly (eFlash, BCD) or Process Integration
Experience in program management
Effective presenter and communicator with strong oral and written English abilities.
Full time 1700006D /
 Physical Design Engineer (ASIC/SoC/P&R) San Jose  OR
Wider requirement than PDV. Design start from floorplanning to chip implementation: includes Netlist to GDS, scripting skill (TCL/ Python/ Perl), APR/ place & rote/ PnR
Title you can look for: ASIC/ SoC design/ Hardware engineer
Cadence innovus (must have), ICC2
Customer Site support position.
Actual Hands-On work
Ok with MS/PhD new grads, prefer GPA of 3.5+
Full time 200000CL Sr. Layout Engineer Austin Minimum Associate’s degree with 10+ years of experience.
Advance tech nodes.
Full time 2200000X Analog Circuit Design Engineer / Sr. Engineer to Sr. Staff Engineer Austin/
San Jose
7+ years of CMOS circuit design
hands-on experience with matlab, python, C, Verilog, or other scripting languages
familiar with commercial analog circuits and mixed-signal design/layout tools
Experience on high-speed(higher than 5), SerDes, die to die interconnect, or RF circuit exp, Low Power
Full time 2100007G Digital Verification Engineer Austin /
San Jose
Minimum MS degree in EE with 3 + years of direct experience in performing the verification on digital/mixed signal designs.
System Verilog, synthesis timing Design-for-test, Verification architecture.
Experience with UVM type of environment
Full time 2100007F  ASIC Implementation Engineer Austin /
San Jose
Minimum MS degree in EE with 3+ years of direct experience in synthesis, synthesis script, timing closure, and APR.
Full time 2100005E Sr. Frontend Engineer San Jose Minimum Master Degree in Electrical Engineering or Computer Science
At least 15 years of frontend ASIC design, 10+ years should be ok as well.
Need SDC/Synthesis experience.
Full time 2100004U Senior Design Verification Engineer San Jose MS/PhD in EE or ECE. Less than 10 years of experience.
Strong hands on experience with architecting and developing IP/SoC level verification using system Verilog
Knowledge in coverage driven testbench
ok with new grads, but need to have strong programming skills (Python, TCL, C++)
Full time 2100004Q Senior and Junior Physical Design Verification Engineer San Jose Verification experience with a strong interest in doing PD verification and fix DRC/LVS/EMIR, etc.
Should still have PD background, not a Verification Engineer.
2nd half SoC Physical Design.
Cadence innovus (preferred) & Synposis in ICC2 & Mentor Calibor -> for chip implementation
Cleanup part for chip tape out.
N28 technology at least
* PDV is a typical requirement for PD engineer. Any chip company who has PD engineer
* Fully onsite position
* Customer onsite support
Full time  2100002I Layout Engineer San Jose At least AA degree with minimum 5 years of direct memory and layout experience.
BS degree with minimum 2-3 years of direct memory and layout experience.
Full time 200000EI System Benchmarking Engineer San Jose/ Austin MS or PhD degree with at least 3 years of relevant experience
Keywords: system-level integration, benchmarks , performance analysis, cache hierarchy, 3D stacking
Full time 200000EB Standard Cell Circuit Engineer San Diego MS or PhD degree with at least 3 years of relevant experience.
Full time 200000CZ Sr. Physical Design Engineer Austin Minimum MS or PhD degree and minimum of 3 years of working experience.
Full time 200000AF Digital Design Engineer Austin /
San Jose
Minimum 3 years of RTL (Digital Design) experience.
Keywords: FPGA, RTL, ASIC, familiar with Analog, frontend design (but has to be within VLSI/ASIC domain area), RTL coding, customer design experience. Serdes/ DDR communication, broadband, highspeed.
Full time 200000CK Sr. Layout Engineer (Analog & Mixed Signal) San Jose At least AA degree with 20 yrs. exp, BS preferred. Advance nodes experience (min. 14nm or 16nm)
Full time 19000071 Sr. Engineer ASIC Physical Design San Jose/ Austin MS in EE/CS
ASIC/chip Tapeout pressure
scripting skills as TCL, Perl, Python
at least 2 years of related industry experience
Full time 200000A0 ASIC SYN & Timing Flow Engineer San Jose at least 2 years of related industry experience.
Full time 2000007Q Library, Technology & Design Flow Co-Optimization Engineer Austin  MS/PhD in EE or CE
5+ yrs exp. hands on w/ RTL2GDSII/supporting SoC design
Expert w/ Synopsys ICC/ICC2 or Candence EDI/Innovus
Strong problem solving skills
Good communication skills
Full time 200000AE Standard Cell Library Design Engineer Austin Circuit design, Layout design, optimization, extraction, characterization
No New Grads
Full time 1900004T Senior Physical Design Engineer (Block/SoC APR) San Jose Physical implementation experience on RTL2GDS or Netlist2GDS. 3-8 years of experience.
Full time 2200000Y SRAM Design Characterization/Validation Engineer Austin BS EE w/ 3+ yrs exp. in compiler memory development
Verification tools: ESP-CV, InSight
Characterization Tools: Synopsys Nanotime, Cadence Liberate (LVF)
Scripting Flow design and maintenance
Time and Power, Race condition, margin characterization, analysis.
Basic knowledge of SRAM
Full time 2000007K SRAM Design Engineer Austin Bachelor’s Degree with min. 5 years, Master’s Degree with min. 3 years experience in compiler memory
Full time 1800001Y/ 1700006H SRAM Design Engineer San Jose Bachelor’s Degree with min. 5 years, Master’s Degree with min. 3 years experience in compiler memory, PhD with 0 experience is ok (But experience in research project)
Full time 1900008I Custom Design Flow Methodology Engineer San Jose Relevant/adequate experience in PDK related knowledge with advanced nodes.
Looking for 5~ 10 Yr. exp.
Full time 1900007D ASIC Design Methodology & Flow Application Engineer San Jose Mandarin Speaker preferred
Full time 19000065 Sr. DFT Design Engineer San Jose less than 20 years of experience
ok with new grads, but need to have strong programming skills (Python, TCL, C++)
Full time 210000AO Program Manager (Customer Support) San Jose 5+ yrs exp. in IC Design/Chip implementation, Circuit Design, Digital Design, design methodology