Date: Saturday July 13th, 2019
Time: 12:00 pm to 5:10 pm
Venue: SEMI Milpitas, 673 S Milpitas Blvd, Milpitas, CA 95035
Attire: Business Casual
Topic: Breaking the Memory Wall, the AI Bottleneck
12:00pm – 1:00pm Registration & Networking
1:00 pm – 1:10pm Welcome from Semi & CASPA chairman
1:10 pm – 1:40pm Ajit Manocha, CEO, SEMI
1:40 pm – 2:10pm Steven Woo, Fellow and Distinguished Inventor, Rambus
2:10 pm – 2:20pm Break
2:20 pm – 2:50pm Sayeef Salahuddin, Professor of EECS Dept., UC Berkeley
2:50 pm – 3:20pm Naveed Sherwani, President and CEO, SiFive
3:20 pm – 3:50pm Bill En, Sr. Director, AMD
3:50 pm – 4:00pm Break
4:00 pm – 5:00pm Panel Session : Breaking the Memory Wall, the AI Bottleneck
Lung Chu, President, SEMI China (Moderator)
Nilesh Gharia, CTO, Numem
Robert Fan, President, SiliconMotion USA
5:00 pm – 5:10pm Closing Remark
The theme of the symposium is “Breaking Memory Wall, the AI bottleneck”, it covers challenges in Artificial Intelligence, how to overcome and the impact in the future of semiconductor industry. The symposium will enhance participating company’s leadership for the revolution happening in our industry around semiconductor and AI.
President and CEO, SEMI
Speech title: Semiconductor Market Trends in the Digital Era
Bio: Ajit Manocha is the president and CEO of SEMI. Headquartered in Milpitas, California, SEMI is the global industry association serving the electronics manufacturing supply chain. Manocha, an industry leader has over 35 years of global experience in the semiconductor industry.
Manocha was formerly CEO at GLOBALFOUNDRIES, during which he also served as vice chairman and chairman of the Semiconductor Industry Association (SIA). Earlier, Manocha served as EVP of worldwide operations at Spansion. Prior to Spansion, Manocha was EVP and chief manufacturing officer at Philips/NXP Semiconductors. He began his career at AT&T Bell Laboratories as a research scientist where he was granted several patents related to microelectronics manufacturing.
Manocha is active on global advocacy issues and has served on the President’s committees for “Advanced Manufacturing Partnerships” and the President’s Council of Advisors on Science & Technology (PCAST) during the last 4+ years.
Sr. Director, AMD
Talk Title: Advanced Computing and Memory Innovation for AI
Abstract: The exponential growth of data and the AI to intelligently process that data has pushed the limits of memory capability. The growth of the Internet of Things (IOT) and increasing sophistication of AI tools to provide end user results from rapidly expanding databases, the need for enhanced memory will only grow. With Moore’s law scaling challenges, memory scaling is falling behind computational logic’s capabilities and need. New innovations are needed to increase memory capability to support AI requirements.
Bio: 23 years of experience in the Semiconductor Industry ranging from silicon wafer R&D, process technology, circuit design and foundry technology with over 65 patents and 30 publications. He graduated from Univ. of California Berkeley with a Ph.D in Electrical Engineering and Computer Sciences in 1996. He is currently Sr Director at Advanced Micro Devices overseeing Foundry technology from initial R&D through production for all AMD products.
Fellow and Distinguished Inventor, Rambus Inc.
Talk Title: Breaking Down the AI Memory Wall
Abstract: Rapid advances in artificial intelligence have re-energized the semiconductor industry, with numerous companies developing AI-specific silicon aimed at providing ever-higher levels of performance and power efficiency. Although these chips and systems are still in their infancy, they have already broadened AI’s reach and its impact on society. As our increasingly connected world evolves, AI continues to evolve as well. But several critical challenges await chip and system designers as our industry strives to meet the relentless demands for more performance and better power efficiency. Among the most critical of these challenges are memory system bottlenecks that serve as a stark reminder of the processor-memory gap that has impacted processor design for the last few decades. With Moore’s Law slowing and Dennard scaling finished, the industry has turned to domain-specific silicon to improve performance and power consumption. Utilizing a variety of techniques, specialized neural network processors have demonstrated tremendous improvements in performance and power efficiency on these workloads. But they have also exacerbated the decades-old processor memory gap, creating an “AI-memory gap” that threatens the continued progress of AI silicon. In this talk I’ll discuss some of these challenges, as well as potential ways to support the continued progress of silicon for AI applications.
Bio: Steven Woo is a Fellow and Distinguished Inventor at Rambus Inc., working in Rambus Labs on technology and business development efforts across the company. His current focus is on technology and memory systems for accelerators and modern computing infrastructures, including machine learning systems, data centers, and advanced computing systems. Since joining Rambus, Steve has worked in various roles leading architecture, technology, and performance analysis efforts, and in marketing, strategy, and product planning roles. Steve received PhD and MS degrees in Electrical Engineering from Stanford University, and Master of Engineering and BS Engineering degrees from Harvey Mudd College.
Prof. Sayeef Salahuddin
Electrical Engineering and Computer Sciences, University of California Berkeley
Speech Title: Negative Capacitance Transistors
Bio: Sayeef Salahuddin is a professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. Salahuddin is mostly known for the discovery of Negative Capacitance effect. His work has focused primarily on conceptualization and exploration of novel device physics for low power electronic and spintronic devices. Salahuddin received the Presidential Early Career Award for Scientist and Engineers (PECASE) from President Obama in 2016. Salahuddin also received a number of other awards including the NSF CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Air Force Office of Scientific Research (AFOSR) and the Army Research Office (ARO) and best paper awards from IEEE Transactions on VLSI Systems and from the VLSI-TSA conference. In 2012, Applied Physics Letters (APL) highlighted two of his papers among 50 most notable papers among all areas published in APL within 2009-2012. Salahuddin is a co-director of the Berkeley Device Modeling Center (BDMC) and Berkeley Center for Negative Capacitance Transistors (BCNCT). Salahuddin is also a co-director of ASCENT, a multi university research center jointly supported by SRC/DARPA. He served on the editorial board of IEEE Electron Devices Letters (2013-16) and was the chair of the IEEE Electron Devices Society committee on Nanotechnology (2014-16). Salahuddin is a Fellow of the IEEE.
Abstract: A transistor looking from the gate essentially acts as a series combination of two capacitors: the gate oxide capacitor and the channel capacitor. When the gate oxide is an appropriate ferroelectric, this series combination can stabilize the ferroelectric material at a state of negative capacitance. At this state, the total capacitance of the series combination is enhanced, leading to more charge at the channel at the same voltage. This boost of charge, in turn, leads to larger current at the same gate voltage. Therefore, Negative Capacitance could reduce supply voltage requirement in transistors, leading to significantly improved energy efficiency. In the recent years, many groups around the world, both in academy and in the industry, have demonstrated the fundamental effect and the Negative Capacitance Transistors. In this work, we shall describe the physical origin of the negative capacitance effect as well as experimental measurement of negative capacitance transistors which confirm the improved gate control expected from the Negative Capacitance effect.
President and CEO, SiFive.
Speech title: Domain Specific Architectures Accelerating Embedded AI for Edge Devices
Bio: Dr. Naveed Sherwani, Ph.D is Chief Executive Officer at SiFive, Inc. since August 15, 2017 and its President since May 2019. Dr. Sherwani serves as the Chief Executive Officer and President of PeerNova, Inc. Dr. Sherwani has over 25 years of experience in Entrepreneurship, Technical Engineering and General Management. He co-founded Open-Silicon, Inc. in 2003 and served as its Chief Executive Officer and President. He also founded Brite Semi. Dr. Sherwani was the founder and General Manager of Intel Microelectronics Services. He served in various technical and managerial positions in Intel for 9 years. He Co-architected the Intel microprocessor design methodology and environment, that has been used in various leading microprocessors. Prior to Intel, Dr. Sherwani served as a Consultant for various telecommunications and computer companies, mainly focused on ASIC style design flow and cell library design to improve time-to-market. He also served as a Professor at Western Michigan University, where his research concentrated on VLSI Physical Design Automation, combinatorics and graph algorithms. He served as Chairman Emeritus of Open-Silicon, Inc. Dr. Sherwani served as the Chairman of Brite Semiconductor Inc. He serves as the Head of Advisoy Board of CoinTerra Inc. Dr. Sherwani serves as a Director for the Global Semiconductor Alliance (GSA) (formerly, the Fabless Semiconductor Association). He serves as a Director of PeerNova, Inc. He serves as a Director of Brite Semiconductor Inc. and Touchstone Semiconductor, Inc. He served as a Director of Open-Silicon Inc. and Integration Associates Inc. He served as a Member of the Technical Advisory Board of Pyxis Technology Inc. In 15 years, he is a frequent speaker at DAC, ICCAD, International Conference on VLSI Physical Design Automation. Dr. Sherwani is a Noted Author, with 4 books, focused on Physical Design Automation, in circulation and widely used at major Universities around the world. In addition, he has Authored or Co-Authored 3 books and over 100 articles on various aspects of Physical Design Automation and ASICs. Dr. Sherwani received his Ph.D. from University of Nebraska-Lincoln.
Panel: Breaking the Memory Wall, the AI bottleneck
President, SEMI China
Lung Chu currently serves as Corp VP and President of SEMI China. He is in charge of the overall operation of SEMI’s programs, committees, products, including SEMICON China event which attracted 91,000 people this year.
Lung has over 30 years of experience in the industry. Prior to SEMI, Lung served as regional president of GUC, Cadence, Magma in charge of Asia Pacific and China. He has been based in Shanghai for 15 years, but worked in Silicon Valley for many years as executives of KLA-Tencor, TMA, Cadence, Apple, and Philips Semi.
Lastly but not leastly, Lung also served as Chairman of CASPA in 2002-2003, and is still the chairman of CASPA chapters in China and Taiwan. So he is truly an old friend of CASPA with passionate in serving the IC industry.
Panel Speaker 1:
Co-Founder/CTO at Numem
Nilesh has 20+ years of experience in the semiconductor industry with a diverse background in semiconductor design and product development. Nilesh is currently Co-Founder/CTO at Numem. Prior to Numem, Nilesh was Founder/CEO of NVMEngines which was later renamed to Numem. Nilesh was part of the startup team at NetLogic Microsystems which went IPO in 2004, and was later acquired by Broadcom in 2012, which in turn was acquired by Avago in 2016 for $37B. He was also the 1st Engineer at Lanstar Semiconductor, which also went IPO. Nilesh worked in Virtual Silicon Technology, and was responsible for team development and product design. His expertise includes startups, emerging memories, memory compiler development, MRAM technologies, semiconductor IP development, network processors, and team/project management. Nilesh holds a Masters in Electrical Engineering from the New Jersey Institute of Technology and has a portfolio of 14 US issued patents.
Panel Speaker 2:
President, SMI USA
Mr. Fan has served as President of SMI USA in charge of Silicon Motion’s business operations in the Americas and Europe. In this role, he is responsible for driving expanded business with the company’s client and enterprise SSD solutions. He also oversees corporate marcom and PR efforts as well as the graphics business. Mr. Fan has over 25 years of sales and marketing experience and joined Silicon Motion in May 2013. Prior to Silicon Motion, Mr. Fan served in executive management roles at Spansion, IDT, Staktek, Berkana Wireless (acquired by Qualcomm) and Resonext (acquired by RF Micro Devices). He also spent over nine years at Intel in sales, marketing and management positions. Mr. Fan currently serves as a board member of Monte Jade West Technology Association, an executive mentor and board member in the Monte Jade mentorship program and is a board member of numerous startups. Mr. Fan holds a BS in Electrical Engineering from the University of California, Berkeley and MSEE from Santa Clara University, and completed the General Management Executive Program at McCombs School of Business, University of Texas.
Panel Speaker 3: TBD
Panel Speaker 4: TBD