CASPA 2021 Summer Symposium

111-3

CASPA 2021 Summer Symposium

A Renaissance for Semiconductors

Date: July 24, 2021, 2:00PM — 6:00PM PDT
Registration link: click here
Zoom link: https://us06web.zoom.us/j/88907545590
Meeting ID: 889 0754 5590

CASPA Summer Symposium

A Renaissance for Semiconductors
2:00pm – 2:10 pm
Welcome Remarks
2:10pm – 2:20pm
Introduction of CASPA
2:20pm – 2:50pm
Rick O'Connor, President & CEO, OpenHW Group
2:50pm – 3:20pm
Rishi Chugh, VP of Marketing, Cadence Design Systems
3:20pm – 3:50pm
Song Han, Assistant Professor, Dept. of EECS, MIT
3:50pm – 4:20pm
Shelly Van Dyke, VP & Head of Strategy, Automotive business, NXP

Ho Wai Wong-Lam, VP of Strategy, NXP
4:20pm – 4:50pm
Chloe Jian Ma, Vice President, China GTM, IoT & Embedded, ARM
4:50pm – 6:00pm
Panel Discussion

Ho Wai Wong-Lam, VP Strategy, NXP Semiconductors

Kelvin Low, General Manager, SEMIFIVE USA

Jeremy Chen, Engineering Manager at Facebook FRL

Ian Wang, Technology Director, SmartGiant Technology

Jim Yastic, Director of Technical Marketing, Macronix

Moderator: William Kou, Director of Sales, ProteanTecs
6:00pm
Closing Remarks

Rick O’Connor

President and CEO at OpenHW Group

Title: CORE-V: Industrial Grade Open-Source RISC-V Cores

Abstract: The CORE-V family is an OpenHW Group project to develop, deploy, and execute pre-silicon functional verification and SoC based development kits of the CORE-V family of open-source RISC-V cores. Written in SystemVerilog, the CORE-V open-source IP matches the quality of IP offered by established commercial providers and is verified with state-of-the-art, auditable flows.

CORE-V cores are verified using CORE-V-VERIF a silicon-proven, industrial-grade functional verification platform. CORE-V-VERIF has been used to execute a complete verification cycle of the CORE-V CVE4 (CV32E40P 4-stage embedded class core) and is currently being used to execute verification of additional CVE4 variants as well as CVA6 32 and 64bit 6-stage embedded class cores. CORE-V-VERIF leverage verification components developed by the RISC-V community and will be continuously maintained and enhanced to integrate the latest best-practices and technology for the verification of future CORE-V cores such that CORE-V cores can be used in high-volume production SoCs.

Bio: Rick O’Connor is Founder and serves as President & CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where HW and SW designers collaborate in the development of open-source cores, related IP, tools and SW such as the CORE-V Family of open- source RISC-V cores. Previously Rick was Executive Director of the RISC-V Foundation which was launched by Rick in 2015. Today, under RISC-V International, the RISC-V ecosystem consists of more than 400 members building an open, collaborative community of software and hardware innovators powering processor innovation. With many years of Executive level management experience in semiconductor and systems companies, Rick possesses a unique combination of business and technical skills and over Rick’s career, he was responsible for the development of dozens of products accounting for over $750 million in revenue. Rick holds an Executive MBA degree from the University of Ottawa, Canada and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College, Canada.

Chloe Jian Ma

Vice President, China GTM, IOT & Embedded, ARM

Bio: Chloe Jian Ma is VP of China Go-To-Market for the IOT and Embedded Line of Business at Arm. In this role, Chloe is responsible for strengthening and expanding Arm products, solutions and ecosystem for China market so that the next wave of innovations in AIoT and embedded intelligence happen on Arm platform. She joined Arm from the RISC-V world, where she worked for both SiFive and StarFive (SiFive’s China JV) and had her hands full with many aspects of the business from global technology partnership/ecosystem building, to GTM strategy, to fundraising and running a regional subsidiary. Chloe’s experience in semiconductor industry also included Mellanox and Intel, where she led the GTM of cloud networking and compute solutions into the hyperscale Internet and Cloud service provider segment. Prior to entering the semiconductor industry, Chloe assumed engineering and marketing leadership roles in the networking industry at Juniper Networks, Huawei and Cisco Systems. To close the full loop, her 1st job was with Wind River in real-time embedded OS with a vision to make everything smart! Chloe received an MBA degree from Wharton, an MSEE from University of Southern California, and a BS in Electronics from Peking University in China.

Rishi Chugh

VP of Marketing, Cadence Design Systems

Bio: As VP of Marketing , Rishi Chugh heads the IP division of Cadence Design, responsible for interface IP (Memories & SerDes) as well as Analog Mixed Signal business. Prior to joining Cadence, Mr. Chugh held Sr. Director role at Cavium, managing their Data Center Processor division and was responsible for the ARM server product line. Prior, Mr. Chugh has held Product Marketing role at Broadcom’s Data Center switch product line managing the Trident switch product line. Mr. Chugh has over 20 years of industry experience working at Cavium, Broadcom, Altera, LSI and Artisan Components (acquired by ARM). Mr. Chugh holds a Bachelor of Electronics degree from the University of Bombay in India, a Master’s of Science degree in Electrical Engineering from San Jose State University and an MBA from Santa Clara University

Song Han

Assistant Professor, MIT EECS

Title: TinyML and Efficient Deep Learning with Limited Silicon Resource

Abstract: As there’s a global shortage of silicon chips, it is crucial to enable deep learning on resource-constrained devices. I will describe model compression techniques including pruning and quantization to reduce the model size, then AutoML and hardware-aware neural architecture search techniques to synthesize small and compact neural networks given latency/memory constraints, which enables Imagenet classification on a microcontroller that has only 1MB of Flash. Finally I’ll describe co-designing deep learning accelerator architecture together with the neural network topology. I will conclude by discussing the efficient techniques for various deep learning applications.

Bio: Song Han is an assistant professor at MIT’s EECS. He received his PhD degree from Stanford University. His research focuses on efficient deep learning computing. He proposed “deep compression” technique that can reduce neural network size by an order of magnitude without losing accuracy, and the hardware implementation “efficient inference engine” that first exploited pruning and weight sparsity in deep learning accelerators. His team’s work on hardware-aware neural architecture search that bring deep learning to IoT devices was highlighted by MIT News, Wired, Qualcomm News, VentureBeat, IEEE Spectrum, integrated in PyTorch and AutoGluon, and received many low-power computer vision contest awards in flagship AI conferences (CVPR’19, ICCV’19 and NeurIPS’19). Song received Best Paper awards at ICLR’16 and FPGA’17, Amazon Machine Learning Research Award, SONY Faculty Award, Facebook Faculty Award, NVIDIA Academic Partnership Award. Song was named “35 Innovators Under 35” by MIT Technology Review for his contribution on “deep compression” technique that “lets powerful artificial intelligence (AI) programs run more efficiently on low-power mobile devices.” Song received the NSF CAREER Award for “efficient algorithms and hardware for accelerated machine learning” and the IEEE “AIs 10 to Watch: The Future of AI” award.

Ho Wai Wong-Lam林可蕙램호와이

VP Strategy, NXP Semiconductors

Bio: Ho Wai is a technology and semiconductor veteran for 30+ years. She started with Philips Research in The Netherlands, and moved to US to join Philips Semiconductors, which became NXP Semiconductors. She has worked in a wide range of disciplines, from research to R&D, from engineering management to marketing and business development, and since 2013 in strategy. In her role as VP strategy, she supports the analog, power and interface strategy development at NXP, which spans a wide range of applications including automotive, mobile, and computing. Since 2020, she represents NXP as a sponsor and a volunteer judge at Extreme Technology Competition (XTC) which is a worldwide competition for startup companies in the theme of “Technology for Good”.

Ho Wai graduated in Electrical Engineering from the University of Hong Kong, and got her master’s degree in Eindhoven, The Netherlands, through a Philips scholarship. She is (co-)author of 13 granted patents, and a dozen peer-reviewed journal papers. Ho Wai is an engineer at heart and a strategist by profession. She is a team player, team leader and a team builder. She believes in Tech for Good – doing well while doing good.

Shelly Van Dyke

VP & head of Strategy Automotive Processing business and the Automotive segment, NXP

Bio: Shelly Van Dyke is VP & head of Strategy for NXP’s Automotive Processing business and the Automotive segment. She has over 30 years of experience in engineering, strategy and strategic finance for the semiconductor industry and the technology supply chain, particularly in automotive and industrial segments. Career highlights include the start-up of the first Motorola 200mm fab, Freescale’s two Initial Public Offerings, serving on the Board of the World Semiconductor Trade Statistics industry association, the NXP-Freescale merger integration, and chartering the Financial Planning & Analysis department at National Instruments. She has a Bachelor’s degree in Chemical Engineering from UT Austin, and a Master’s in Business Administration from Regis University, and lives in Austin, Texas.

Panelists:

Kelvin Low

General Manager, SEMIFIVE US Inc

Bio:

 

Kelvin Low joined SEMIFIVE as the General Manager of SEMIFIVE US Inc with broad-ranging experience in various silicon foundries and design ecosystem. Mr. Low is responsible for SEMIFIVE US Inc’s operations and business expansion, which includes Sales, Business Development, Field Technical Support and Program Management functions. He is also responsible to extend SEMIFIVE’s business reach to other worldwide regions. Prior to SEMIFIVE, Mr. Low held key Technical, Marketing and Sales executive positions at Arm Inc, Samsung Foundry and GLOBALFOUNDRIES. He was also recently the vice president of marketing, strategy and overseas sales at SMIC. Mr. Low started his career at Chartered Semiconductor Manufacturing as a process integration engineer where he led development of logic, mixed signal, RF, CIS and NVM processes. Mr. Low also had additional responsibilities as the marketing lead in the IBM joint development alliance and Common Platform. Mr. Low received his bachelor’s degree in electronics and electrical engineering with First Class Honors from the National University of Singapore.

Jeremy Chen

Engineering Manager at Facebook FRL

Bio:

 

 

Jeremy Chen leads one of the Systems EE Teams inside FRL, responsible for Product Key Technology Development and New Technology Introduction, and oversees the product line’s Technology Roadmap. In his previous role with Apple, he served as Power Management IC Architect and Power/Analog lead for iPhone Team. Jeremy has years of experience leading custom silicon definition, development, and integration for some of the world’s most popular and successful consumer products. He also has a deep understanding of SiP Technology and Harsh Environment Electronics design based on previous experience in the Oil & Gas Industry. Jeremy holds a master’s degree in Electrical and Computer engineering from Texas A&M University and a bachelor’s degree in Electrical Engineering from Zhejiang University.

Ian Wang

Technology Director, SmartGiant Technology Co. Ltd.

Bio:

 

Mr. Ian Wang has 22 years of experience in semiconductor industry. He is currently Technology Director and Marketing Manager at SmartGiant Technology Corporation Limited in Santa Clara, California, USA. Prior to SmartGiant, he was an Engineering Manager at Intel Programmable Solutions Group (PSG) in the field of FPGA Design Verification. Before Intel, he worked as design engineer for Alcatel-Lucent Inc. in the field of ASIC design.  Mr. Wang received a Master of Electrical Engineering degree from Carleton University and a Master of Science in Physics from McGill University, both in Canada. He also earned his Bachelor of Science in Physics from Nanjing University in China. Mr. Wang served as a member of the Board of Directors for CASPA since 2017. He acted as the Head of Publication in 2018, and the Head of Symposiums in 2019 and 2021. Mr. Wang has multiple scientific publications in Physics and Microelectronics. He served as a Technical Paper Reviewer for IEEE Transactions on Circuits and Systems II.

Jim Yastic

Technical Marketing | Business & Market Development | Ecosystem Development & Management, Macronix

Bio:

Jim Yastic is a Technical Marketing Manager at Macronix, responsible for ecosystem, market, product, and business development. With 30 years of experience in the high technology sector, his previous roles include engineering, product marketing management, and business development for organizations focused on semiconductor, communications, and embedded software markets. Jim holds a MBA degree from St. Edwards University in Austin, and a BSEET and Computer Science degree from Chapman University in Orange CA.