The 2022 IEEE Electronic Design Process Symposium (EDPS)
29th edition of 2022 IEEE EDPS continues the tradition of fostering vibrant exchange of ideas among top thinkers from industry and academia in the areas of Electronic Design Automation, Chip and System Designs and many more. It will be held at SEMI facility in Milpitas, CA on Oct 6 & 7, 2022. We have presentations from Intel, Ericsson, Ansys, Synopsys, Cadence, Nvidia among many others.
The conference registration includes breakfast and lunch on both days and dinner on Oct 6. Additionally, we will be giving away Bose QuietComfort Earbuds to 2 attendees chosen at random during the conference!
Don’t wait to grab this amazing opportunity to learn and network! More information is available below and at https://ieee-edps.com
29th IEEE EDPS
Ramond Rodríguez
General Chair, IEEE EDPS 2022 (October 6th and 7th)
Registration: https://
The 2022 IEEE Electronic Design Process Symposium (EDPS) is in its 29th year and continues to foster the free exchange of ideas among the top thinkers and thought leaders who focus on how chips and systems are designed in the electronics industry. This year the EDPS executive committee has decided to return this year’s symposium to a live event scheduled for October 6th and 7th, 2022 at the SEMI facility in Milpitas, CA.
EDPS provides a forum for this cross-section of the design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.
As designs get more complex, the design, test and manufacturing cycles are getting longer and more intertwined with each other. Therefore, EDPS has been expanding its scope and looking beyond the classical design processes. EDPS 2022 will continue to cover test, manufacturing, validation, and security issues as they pertain to the design of chips/systems. Each session of EDPS will offer a holistic view of design, test, validation, and manufacturing issues.
This year we will focus on Smart Design and Manufacturing. We will look at new developments in systems approach to design and manufacturing, and work using system-level techniques to reach HVM in a shorter amount of time. New techniques such as Silicon Photonics, Heterogeneous Integration, Advanced Packaging, 5G/6G, and Machine Learning for improving design processes will be presented. As CAD applications continue to expand in the medical field, we have also added a special session on CAD for Medical. We have speakers from industry discussing integration of new techniques in their solutions. We also have speakers from academia showcasing how some of the latest research is making it into design and manufacturing processes and associated tools.
We have prominent keynotes from industry veterans on design and manufacturing trends and requirements that we will see over next five to ten years. Our keynote speakers are:
Bob Brennan, Intel Corporation – System Foundry and Chiplet Revolution
Gang Qu, UMD/NSF – VoltJockey: Software-Controlled Voltage-Induced Hardware Fault Injection Attacks
Shekar Kapoor, Synopsys – Realization of Multi-Die System Designs in the SysMoore Era
John Park, Cadence – As Chips Become Systems; Design Challenges for 3D-IC
Xi-Wei Lin, Synopsys – System-Technology Co-optimization
Chris Rowen, Cisco – Systems Drive Silicon: How Machine Learning is Reshaping Chip-land
Mallik Tatipamula, Ericsson – 5G -> 6G Transition
Phil Sohn, Keysight – Digital Twins for 5G and 6G
Yorgos Koutsoyannopoulos, Ansys – Signal Integrity and Electromagnetic Analyses Techniques for High-speed Interconnects in 3DICs
Jasper VanWoudenberg, Riscure – Embedded Security in a 5G World
Prith Banerjee, Ansys – Leveraging Computer Models and Simulation to Make You Live Longer and Healthier
Kerim Genc, Synopsys – Synopsys Simpleware for 3D Image-based Analysis in Life Sciences, Materials, and Industrial Applications
Sanjay Choudhary, Nvidia – Modulus: A physics-ML framework with applications in Industrial, Weather and Climate, and Life-Sciences
The event will be held conveniently at the SEMI facility in Silicon Valley and provide a forum for EDA, design, wafer fab and packaging/test experts to address both design and manufacturing challenges. To register go to https://edps2022.