The 2023 IEEE Electronic Design Process Symposium (EDPS) is in its 30th year and continues to foster the free exchange of ideas among the top thinkers and thought leaders who focus chip and system design in the electronics industry. This year the IEEE EDPS will be a live event scheduled for October 5th and 6th, 2023 at the Synopsys facility in Sunnyvale, CA.
EDPS provides a forum for this cross-section of the design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.
As designs get more complex, the design, test and manufacturing cycles are getting longer and more intertwined with each other. IEEE EDPS has been expanding its scope and looking beyond the classical design processes. EDPS 2023 will continue to cover test, manufacturing, validation, and security issues as they pertain to the design of chips/systems. Each session of EDPS will offer a holistic view of design, test, validation, and manufacturing issues.
This year we will focus on Silicon to System – Smart Design and Manufacturing. We will look at new developments in the systems approach to design and manufacturing, and work using system-level techniques to reach HVM in a shorter amount of time. New techniques such as Systems Design, Heterogeneous Integration, Advanced Packaging, Artificial Intelligence/Machine Learning, and Design for Trust for improving design processes will be presented. As CAD applications continue to expand to improve reliability, we have also added a special session on Reliability, Availability, and Serviceability. We have speakers from industry discussing integration of new techniques in their solutions. We also have speakers from academia showcasing how some of the latest research is making it into design and manufacturing processes and associated tools.
We have prominent keynotes from industry veterans on design and manufacturing trends and requirements that we will see over next five to ten years. Our keynote speakers are:
Rob Aslett, Si2 – Si2 Value, Velocity, and You
Prof. Sung-Kyu Lim, Georgia Tech – Machine Learning Powered VLSI Physical Design Automation
David Pan, UTA – AI for Chip Design & EDA: Everything, Everywhere, All at Once
Lav Vashney, UIUC – Trustworthy Generative AI
The event will be held at the Synopsys facility in Silicon Valley and provide a forum for EDA, design, wafer fab and packaging/test experts to address both design and manufacturing challenges. To register go to https://2023-ieee-edps.eventbrite.com. For a list of speakers and abstracts visit https://www.ieee-edps.com/program1.html.