CASPA 2020 Annual Conference: Next Wave of Semiconductor Innovation

Past Symposium Events October 17, 2020

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When: Oct 17, 2020 01:00 PM Pacific Time (US and Canada)

Topic: CASPA 2020 Annual Conference: Next Wave of Semiconductor Innovation

Registration link: Click here

Join Zoom Meeting: https://zoom.us/j/98701526646?pwd=NUN2Mm84ekxrMWdNVlRTNSthbWI3dz09

Meeting ID: 987 0152 6646

YouTube live stream: https://youtu.be/a0XaiO5EL1g

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Next Wave of Semiconductor Innovation

Abstract: Semiconductor industry history consists of waves of growth. Each one was driven by a new application like mainframe computers, minicomputers, personal computers, wireless communications, etc. We are entering a new wave of growth that is broadly driven by the changing role of data in society. Effects of this evolution are seen in new neuromorphic computing chips for machine learning, components to enhance edge processing of data and other AI applications. Central to this wave of growth is the need to secure the data. While it is important to develop improved defenses from data center hacking, as well as protections from embedded trojans in applications, operating systems and chips, the ultimate solution is to secure the data itself. Fully homomorphic encryption is the only known approach to do this. Dr. Rhines will discuss current waves of semiconductor industry growth and the likely evolution of approaches to data security.

Walden C. Rhines

CEO, Cornami Inc.

CEO Emeritus of Mentor, a Siemens Business

WALDEN C. RHINES is President and CEO of Cornami, Inc., a fabless software/semiconductor company focused on intelligent computing for fully homomorphic encryption and machine learning. He was previously CEO of Mentor Graphics for 25 years and Chairman of the Board for 17 years. During his tenure at Mentor, revenue nearly quadrupled and market value of the company increased 10X. Prior to joining Mentor Graphics, Dr. Rhines was Executive Vice President, Semiconductor Group, responsible for TI’s worldwide semiconductor business. During his 21 years at TI, he was President of the Data Systems Group and held numerous other semiconductor executive management positions. Dr. Rhines has served on the boards of Cirrus Logic, QORVO, TriQuint Semiconductor, Global Logic and as Chairman of the Electronic Design Automation Consortium (five two-year terms). He is also a board member of the Semiconductor Research Corporation and First Growth Children & Family Charities. He is a Lifetime Fellow of the IEEE and has served on the Board of Trustees of Lewis and Clark College, the National Advisory Board of the University of Michigan and Industrial Committees advising Stanford University and the University of Florida. Dr. Rhines holds a Bachelor of Science degree in engineering from the University of Michigan, a Master of Science and PhD in materials science and engineering from Stanford University, a Master of Business Administration from Southern Methodist University and Honorary Doctor of Technology degrees from the University of Florida and Nottingham Trent University.

Integration Technologies Transforming the World

Abstract: The electronics industry is transforming our world, driven by semiconductor innovation enabling products and applications that are literally changing lives, from health to transportation, from robotics to AI, from edge to cloud, from 5G to beyond. Advances in silicon integration technologies are proving truly revolutionary, where multiple die from multiple sources of varying functionality are being combined to achieve unprecedented performance and operating characteristics. The packaging industry is at the forefront for the enablement of this integration. With a comprehensive tool box leveraging innovative technologies such as 2.5D & 3D die interconnection, high density fan-out, embedded devices, conformal and compartmental shielding, integrated antenna, and more, System-in-Package (SiP) portfolios are constantly being refined and enhanced to support growing demand for next generations of system integration. During his talk, Yin Chang will describe the expanding application landscape, discuss integration technology innovation, and explore how SiP technologies are delivering on their promise of miniaturization, power efficiency, and highest performance yet.

Ingu Yin Chang

Senior Vice President, Sales & Marketing

ASE Group

Ingu Yin Chang is Senior Vice President, Sales & Marketing, at ASE, based in Sunnyvale, California. In his current role, he is responsible for developing and executing sales strategy, while driving marketing activities for ASE’s expanding packaging, systems, and integration solutions portfolio. Prior to joining ASE in 2013, Yin was CEO of Vertical Circuits Inc. (VCI), a company focused on the development of next generation vertical interconnect for next generation silicon integration. Previously, Yin performed a variety of management roles covering sales and operations at Amkor with responsibility for the Greater China region. He has over twenty years of leadership experience in executive management, sales, business development, IP management and strategic alliance. Yin received his material science engineering degree from University of California, Berkeley.

Electronic-Photonic Integrated Systems: From interconnects that accelerate AI to COVID-19 sensors

Abstract: Recently demonstrated monolithic integration of electronics and photonics has enabled a range of new capabilities previously unachievable by electronics alone. Electronic-photonic chiplets used for in-package optical I/O remove communication bottlenecks of high-performance computing and next generation massive-MIMO radios. This same technology interestingly can be used in a range of sensing applications – from LIDAR to biomolecular sensors targeting point-of-care and personalized COVID-19 diagnostics. The breadth of the applications indicates that electronic-photonic technology is positioned to revolutionize the semiconductor industry in the next decade.

UCB Engineering EECS Faculty PortraitsPhotos Copyright Noah Berger / 2013

Vladimir Stojanovic

Professor

University of California, Berkeley

Vladimir Stojanovic is a Professor of Electrical Engineering and Computer Science at University of California, Berkeley. His research interests include design, modeling and optimization of integrated systems, from CMOS-based VLSI blocks and interfaces to system design with emerging devices like NEM relays and silicon-photonics. He is also interested in design and implementation of energy-efficient electrical and optical networks, and digital communication techniques in high-speed interfaces and high-speed mixed-signal IC design. Vladimir received his Ph.D. in Electrical Engineering from Stanford University in 2005, and the Dipl. Ing. degree from the University of Belgrade, Serbia in 1998. He was also with Rambus, Inc., Los Altos, CA, from 2001 through 2004 and with MIT as Associate Professor from 2005-2013. He received the 2006 IBM Faculty Partnership Award, and the 2009 NSF CAREER Award as well as the 2008 ICCAD William J. McCalla, 2008 IEEE Transactions on Advanced Packaging, and 2010 ISSCC Jack Raper best paper awards. He was an IEEE Solid-State Circuits Society Distinguished Lecturer for the 2012-2013 term.

AI and Data-Centric Trends and Opportunities

Abstract: AI and the Data-Centric Revolution have created many opportunities, in hardware and software/applications; for large enterprises and for startups. This talk will provide an overview of the macro trends driving these massive changes in our industry, and survey opportunities in the data center, data analytics, and specific verticals.

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Renxin Xia

Chief of Staff to the CEO

Cadence

Renxin is an executive with 20+ years of engineering and management experience. His experiences range from SOCs for consumer applications to high-end FPGAs, using both ASIC and full custom design flows. Renxin has a proven, successful track record of building organizations and delivering products at both startups and large corporations. Renxin is currently the Chief of Staff to CEO Lip-Bu Tan at Cadence Design Systems. Prior to joining Cadence, he was the first VP of Engineering at SiFive, a leader in RISC-V solutions. Prior to SiFive, Renxin spent 15 years at Altera, where he led design and verification for multiple generations of FPGA’s, culminating in having overall responsibility for Stratix 10, the first flagship family using Intel process. Renxin started his career at ESS Technology and was a co-founder/acting VP of Engineering at Centrality Communications, which was acquired by SiRF. Renxin holds a BSEE and MSEE from Stanford University and an MBA from UC Berkeley Haas School of Business.

Neuromorphic Computing: Brains in Silicon

Abstract: Deep Neural Networks (DNNs) replace the brain’s spike-trains with instantaneous rates that are updated once every time-step. They have proven to be extremely powerful, successfully tackling tasks that were thought to be impossible just a decade ago. The current quest is to deploy them on devices powered by batteries (e.g., mobile phones) or energy-harvesting (e.g., IoT end-points), which require more energy-efficient computing. A promising approach, known as neuromorphic computing, maps DNN’s rate-based abstraction back to the brain’s spike-based abstraction. Since updates are only performed when spikes occur, the computational load is reduced if less than one spike occurs per time-step (per signal). The resulting energy-savings may be negated, however, by overhead incurred in mapping DNNs’ rate abstraction to neuromorphic computing’s spike abstraction (e.g., the network’s size must be increased to preserve performance). I will argue that computing in analog while communicating digitally maximizes spike-based neuromorphic computing’s energy-savings. I will present my group’s progress in designing these mixed-signal neuromorphic chips and in reducing the overhead in mapping DNNs onto them.

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Kwabena Boahen

Professor

Stanford University

Kwabena Boahen received the B.S. and M.S.E. degrees in electrical and computer engineering from the Johns Hopkins University, Baltimore, MD, both in 1989 and the Ph.D. degree in computation and neural systems from the California Institute of Technology, Pasadena, in 1997. He was on the bioengineering faculty of the University of Pennsylvania from 1997 to 2005, where he held the first Skirkanich Term Junior Chair. He is presently Professor of Bioengineering at Stanford University, with a joint appointment in Electrical Engineering. He founded Stanford’s Brains in Silicon lab, which develops silicon integrated circuits that emulate the way neurons compute and computational models that link biophysical neuronal mechanisms to cognitive behavior. His research is interdisciplinary, bringing together the seemingly disparate fields of neurobiology and medicine with electronics and computer science. His scholarship is widely recognized, with over ninety publications to his name. These include a cover story in Scientific American featuring his group’s work on a silicon retina and a silicon tectum correctly “wire together” automatically. (May 2005). He has been invited to give over 70 seminar, plenary, and keynote talks. These include a 2007 TED talk, “A computer that works like the brain”, that has been viewed half-a-million times. He has received several distinguished honors, including a Packard Fellowship for Science and Engineering (1999) and a National Institutes of Health Director’s Pioneer Award (2006). He was elected a fellow of the American Institute for Medical and Biological Engineering (2016) and of the Institute of Electrical and Electronic Engineers (2016). In recognition of his group’s work on Neurogrid (2006-12), an iPad-size platform that emulates the cortex in biophysical detail and at functional scale. As this combination hitherto required a supercomputer, Neurogrid resurged interest in neuromorphic computing. These students went on to lead the design of IBM’s TrueNorth chip. In his most recent research effort, the Brainstorm Project, he led a multi-university, multi-investigator team to co-design hardware and software that makes neuromorphic computing much easier to apply. A spin-out from his Stanford group, Femtosense Inc (2018), is commercializing this breakthrough.

Panel Discussion

David Dutton

CEO

MDC Precision

David L. Dutton serves as MDC’s CEO and is responsible for the leadership, vision and execution of the company. Prior to joining MDC, Dave was Chief Executive Officer and Vice Chairman of the Board of Directors for EDA software company Silvaco. From 2001 to 2013, Dave served as President, CEO and board director of Mattson Technology, a publicly traded semiconductor equipment manufacturer. Throughout his 36-year career, Dave has held various management and engineering positions at leading Silicon Valley high-tech companies, including Intel and Maxim Integrated Products. Dave has served on the Electronic System Design Alliance governing board, the Bay Area Council and the Silicon Valley Leadership Group. Dave holds a bachelor of science degree geology from San Jose State University (San Jose, CA) and an executive MBA from the AEA/Stanford Executive Institute (Palo Alto, CA).

Brandon Wang

Vice President

Synopsys

Brandon Wang is currently a Vice President at Synopsys, overseeing strategic initiatives for the company’s ~$3B core business divisions. Prior to that, he served various executive roles at Cadence in chief strategy office, marketing, and solution engineering. Prior to that, Brandon had over a decade management experiences with both start-ups and larger tech companies including 7 years at Arm, managing the IOIP group. An electrical and computer engineer by training, Brandon holds 10 US patents, and has published at 20+ IEEE conferences, in journal papers and invited talks. Brandon also holds an MBA degree from the Wharton School at the University of Pennsylvania.

Cathy Liu

Director

Broadcom

Cathy Liu, distinguished Engineer and director, currently heads up Broadcom SerDes architecture and modeling group. Previously she worked as R&D director and distinguished engineer in Avago/LSI which acquired Broadcom in 2016. Since 2002, she has been working on high speed transceiver solutions. Previously she has developed read channel and mobile digital TV receiver solutions. Her technical interests are signal processing, FEC, and modeling in high-speed optical and electrical transceiver solutions. She has published many journal and conference papers and holds 20+ US patents. Cathy has demonstrated her leadership roles in industry standard bodies and forums. Currently she serves as a member of the board director of Optical Internetworking Forum (OIF), a member of the board of advisors for the department of Electrical & Computer Engineering (ECE) of University of California at Davis, a member of Signal Integrity Journal editorial advisory board, and the co-chair of the DesignCon technical track of high speed signal processing, equalization and coding.

Norman Chang

Fellow and Chief Technologist

Semiconductor BU, ANSYS Inc.

Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist at Semiconductor BU, ANSYS, Inc.. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds eighteen patents and has authored over 50 technical papers. He is currently in the committee for ESDA-EDA and Si2 AI/ML TAB.

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Robert Fan

President

Silicon Motion Inc USA.

Robert Fan is the President of Silicon Motion Inc. U.S.A. managing the business in the U.S. and Europe regions for Silicon Motion Inc. (NASDAQ: SIMO) – a world leader in NAND storage controller solutions. Robert oversees the largest revenue regions which grew at 37% CAGR in the past seven years. He is also responsible for corporate communications /PR, strategic partnerships and investments, and serves as the General Manager of the graphics business. Prior to Silicon Motion, Robert served in executive positions at companies such as Spansion, IDT and startups like Berkana Wireless (acquired by Qualcomm) and Resonext (acquired by RF Micro Devices) and spent 9+ years at Intel in sales, marketing, and management positions. Robert is currently a board member of Monte Jade Science & Technology Association and volunteers as a mentor as well as an advisory board member in the association’s esteemed executive mentorship program. Robert advises startup companies and also speaks publicly on subjects ranging from technology, leadership and sales. He holds a BS in Electrical Engineering from the U.C. Berkeley, MSEE from Santa Clara University, and completed the General Management Executive Program at McCombs School of Business, University of Texas.

Sung Soo Chung

CTO

QRT Inc.

Sung Soo Chung (IEEE Life Member since 2018) received B.S. degree in Electronics Engineering from Sungkyunkwan University, Seoul, Korea, in 1978 and M.S. degree in Electrical Engineering from Florida Institute of Technology, Melbourne, FL in 1984. He spent 15 and a half years with Cisco Systems Inc., San Jose, CA from 1992 to 2008, where he managed ASIC DFT Technologies Team for over 10 years. Four years prior to his departure, Sung developed company wide SEU test and mitigation processes, ranging from memory to ASIC, device test and qualification criteria, and Soft Error resilience design methodologies as a SEU Technical Lead. As a part of Korean Government’s Brain Scouting Program, he joined Hanyang University as a Research Professor from July 2013 to July 2016, lecturing and researching in the area of SiP/TSV test technology, Single Event Upset (SEU) and SoC reliability. Sung now works for QRT Inc. Korea as a CTO since May 2017 until now. 17 U.S. and Korean patents and has contributed over 50+ technical papers in Boundary-Scan, Logic BIST, Memory BIST, high speed I/O test and SEU test/mitigation and fault injection techniques. Mr. Chung had served as a working group member of IEEE Standards 1149.1, .4, 1500, 1532, JESD89A, and 1149.6, where his patented innovation became a foundation for the Standards. His most recent R&D activities are accelerated radiation test and analysis for ISO26262 Automotive Functional Safety, and soft error mitigation techniques on advanced devices such as Flash, SSD, and Microprocessors.