CASPA Summer Symposium: Breaking the Memory Wall, the AI Bottleneck

Date: Saturday July 13th, 2019

Time: 12:00 pm to 5:10 pm

Venue: SEMI,  673 S Milpitas Blvd, Milpitas, CA 95035

Attire: Business Casual

Topic: Breaking the Memory Wall, the AI Bottleneck

Abstract:  Rapid advances in artificial intelligence have re-energized the semiconductor industry, with numerous companies developing AI-specific silicon aimed at providing ever-higher levels of performance and power efficiency. Although these chips and systems are still in their infancy, they have already broadened AI’s reach and its impact on society.  As our increasingly connected world evolves, AI continues to evolve as well. But several critical challenges await chip and system designers as our industry strives to meet the relentless demands for more performance and better power efficiency. Among the most critical of these challenges are memory system bottlenecks that serve as a stark reminder of the processor-memory gap that has impacted processor design for the last few decades. With Moore’s Law slowing and Dennard scaling finished, the industry has turned to domain-specific silicon to improve performance and power consumption. Utilizing a variety of techniques, specialized neural network processors have demonstrated tremendous improvements in performance and power efficiency on these workloads. But they have also exacerbated the decades-old processor memory gap, creating an “AI-memory gap” that threatens the continued progress of AI silicon. In this talk I’ll discuss some of these challenges, as well as potential ways to support the continued progress of silicon for AI applications.

Bio: Steven Woo is a Fellow and Distinguished Inventor at Rambus Inc., working in Rambus Labs on technology and business development efforts across the company.  His current focus is on technology and memory systems for accelerators and modern computing infrastructures, including machine learning systems, data centers, and advanced computing systems. Since joining Rambus, Steve has worked in various roles leading architecture, technology, and performance analysis efforts, and in marketing, strategy, and product planning roles.  Steve received PhD and MS degrees in Electrical Engineering from Stanford University, and Master of Engineering and BS Engineering degrees from Harvey Mudd College.

Bio: Sayeef Salahuddin is a professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. Salahuddin is mostly known for the discovery of Negative Capacitance effect. His work has focused primarily on conceptualization and exploration of novel device physics for low power electronic and spintronic devices. Salahuddin received the Presidential Early Career Award for Scientist and Engineers (PECASE) from President Obama in 2016. Salahuddin also received a number of other awards including the NSF CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Air Force Office of Scientific Research (AFOSR) and the Army Research Office (ARO) and best paper awards from IEEE Transactions on VLSI Systems and from the VLSI-TSA conference. In 2012, Applied Physics Letters (APL) highlighted two of his papers among 50 most notable papers among all areas published in APL within 2009-2012. Salahuddin is a co-director of the Berkeley Device Modeling Center (BDMC) and Berkeley Center for Negative Capacitance Transistors (BCNCT). Salahuddin is also a co-director of ASCENT,  a multi university research center jointly supported by SRC/DARPA. He served on the editorial board of IEEE Electron Devices Letters (2013-16) and was the chair of the IEEE Electron Devices Society committee on Nanotechnology (2014-16). Salahuddin is a Fellow of the IEEE.

Abstract: As conventional dimensional scaling face significant challenges, it is becoming increasingly difficult to sustain the ongoing march of computing hardware. In this context, our work in the recent years has focused on exploiting new physical phenomena that can potentially offer new functionality. In particular, in this talk I shall talk about the Negative Capacitance Field Effect Transistors (NCFET), which has shown potential for extending the channel length scaling beyond the roadmap by offering immunity to short channel effect and could lead to low standby power SRAM circuts. I shall also talk about non-volatile ferroelectric memory which might allow high density content addressable memory cells close to the processor. Finally, I shall describe some of our recent efforts on Spin Transfer Torque MRAM technology which seems poised to become commercially available as an embedded memory technology.