CIE Seminar – Dr. CT Kao

cadence

Time: 12/11/2021 15:00-16:00PM (Sat)
Venue: Zoom Meeting
Registration: Click Here

Topic:  “Challenge and Response — Thermal and Power Analysis in 3DIC Design”

Interested in 3DIC simulation beyond Moore’s Law? Join us with CT Kao from Cadence on a special talk on thermal and power management.


About this event

As the Moore’s law approaching the physical limit of the critical size on chip, designers are now targeting at building devices in the third dimension, namely, out of the plane where the chip sits. This so-called 3DIC configuration presents a heterogeneous, disaggregated structure where multiple chiplets can be stacked up and placed on a common substrate or interposer. Due to the structural complexity and critical interface connections, the 3DIC design has become the main R&D focus among advanced IC chip designers and foundries alike. Furthermore, when integrating multiple heterogeneous components on one substrate, the designers quickly realize the thermal interaction and temperature distribution among those components under various power sources is one of the gating factors for achieving the desirable performance with optimization.

In this talk the challenges of 3DIC designs from the thermal and power aspects will be briefly addressed, based on the 3DIC configurations presently surfacing in the public domain. Inevitably multi-physics simulation is essential to obtain clear and in-depth understanding of such a complex system, including both steady and transient states analyses based on electrical-thermal co-simulation, Computational Fluid Dynamics (CFD) simulation, IC level power analysis, and so on. Then the ultimate challenge will be to combine these physical simulation modules, forge a holistic solution, and provide the accurate and efficient tool set as the industry advancing into this 3DIC era.

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