Chiplets: Extending Moore’s Law for A New Breed of Semiconductors
Date: Saturday 07/30 2:30pm to 5:30pm
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In response to these opportunities and challenges, CASPA as the world’s largest Chinese American semiconductor professional association, will organize this year’s CASPA Summer Symposium with the theme of “Chiplets: Extending Moore’s Law For A New Breed of Semiconductors“. Summer Symposium is a signature event for CASPA and well attended by the technical professionals and executives from Bay Area and worldwide. We are very pleased to invite you to our 2022 Summer Symposium, scheduled on Saturday 07/30 2:30pm to 5:30pm on the internet via Zoom.
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2022 CASPA Summer Symposium Chiplets: Extending Moore’s Law for A New Breed of Semiconductors |
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| 2:30pm – 2:40 pm | Welcome Remarks and Introduction of CASPA |
| 2:40pm – 3:10pm | Rishi Chugh, Vice President of Product Marketing, Cadence |
| 3:10pm – 3:40pm | Norman Chang, Fellow & Chief Technologist, Semiconductor BU, Ansys |
| 3:40pm – 4:10pm | Joe Wu, Senior Principal Engineer & Manager, Interface Protocol Group, Intel |
| 4:10pm – 4:40pm | Jawad Nasrullah, CEO, Palo Alto Electron and James Wong, CTO, Palo Alto Electron |
| 4:40pm – 5:10pm | Feng Ling, CEO, XpeedIC |
| 5:10pm | Closing Remarks and Prize Draw |
Rishi Chugh
Vice President of Product Marketing, Cadence
As VP of Product Marketing , Rishi Chugh heads the IP division of Cadence Design, responsible for interface IP (Memories & SerDes),Analog Mixed Signal & Tensilica product line. Prior to joining Cadence, Mr. Chugh held Sr. Director role at Cavium, managing their Data Center Processor division and was responsible for the ARM server product line. Prior, Mr. Chugh has held Product Marketing role at Broadcom’s Data Center switch product line managing the Trident switch product line. Mr. Chugh has over 20 years of industry experience working at Cavium, Broadcom, Altera, LSI and Artisan Components (acquired by ARM). Mr. Chugh holds a Bachelor of Electronics degree from the University of Bombay in India, a Master’s of Science degree in Electrical Engineering from San Jose State University and an MBA from Santa Clara University.
Norman Chang
Fellow & Chief Technologist, Semiconductor BU, Ansys
Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist of Electronics, Semiconductor, and Optics BU, ANSYS, Inc. He is also currently leading AI/ML and security initiatives at ANSYS. Prior to Apache, he lead a research group on the research of Power/Signal/Thermal Integrity of chipsets based on VLIW architecture at HP Labs. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds twenty patents and has co-authored over 60 technical papers and a popular book on “Interconnect Analysis and Synthesis” by Wiley-Interscience at 2000. He is currently in the committee for EDPS, ESDA-EDA and SI2 AI/ML SIG, and an IEEE Senior Member.
Joe Wu
Senior Principal Engineer & Manager, Interface Protocol Group, Intel
Zuoguo (Joe) Wu is a Senior Principal Engineer and Manager of an I/O Circuits and Architecture team at Intel. His responsibilities are in the physical layer link architecture and I/O standards and specifications of client and server CPUs and chipsets, including high speed serial interfaces, in-package memory I/O, and low power multi-chip package interfaces. Prior to joining Intel in 2003, he designed computer disk drive, wireless, and optical communication ICs. He has 30+ external and internal publications and 50+ patent applications. Joe received B.S. in Physics from University of Science and Technology of China, and Ph.D. in Electrical Engineering from Texas A&M University.
Jawad Nasrullah
CEO, Palo Alto Electron
Jawad Nasrullah is a chip designer with expertise in chiplets, microprocessors, HW/SW co-design, and SerDes. Previously Jawad was the co-founder and CTO of zGlue, Inc., a Silicon Valley startup that set the direction of chiplet technology and developed a number of heterogeneous integrated circuits. Jawad is now working on the next chapter in heterogeneous integration for Chiplet, Palo Alto Electron, providing R&D services to clients. Jawad has been active with the Chiplet Design Exchange (CDX) workgroup within OCP/ODSA to help catalyze chiplet ecosystems. Before zGlue, Jawad has held leadership positions at Intel, Samsung, Sun Microsystems, and Transmeta. Jawad holds a Ph.D. degree in Electrical Engineering from Stanford University.
James Wong
CTO, Palo Alto Electron
James Wong has over 20 years experience in software design automation, simulation, firmware and hardware design. He has developed a number of IPs and patents in software and hardware applications. He is an active member of Open Compute Project (OCP) and Chiplet Design Exchange (CDX) in Chiplet standardization. He is a co-author of ZEF/ZEFXML for Chiplet exchange format. He led the engineering team to develop the zGlue Chiplet integration and EDA. He has previously worked as a Director, Manager and Engineer at Ma Labs, Oracle, Cisco, and Intel. He holds a Master degree and PhD candidacy in Electrical Engineering and Computer Science from the University of Michigan and National University of Singapore. He is currently working with Jawad on the next generation of Chiplet integration.
Feng Ling
CEO, XpeedIC
Feng Ling is the Founder and CEO of Xpeedic, a leading EDA provider for IC, package, and system designs. Dr. Ling has over 20 years’ industry experiences spanning from corporate Motorola Semiconductor to EDA startups Neolinear (acquired by Cadence), Physware (acquired by Siemens EDA) and Xpeedic. Dr. Ling received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2000.
