CASPA SIG Seminar I: Opportunities and Challenges of EDA Tool (2/25/2023)
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https://us06web.zoom.us/j/87469400953?pwd=VmZZdEFTL2Q2TlIwT0hER2NOWFY0Zz09
Meeting ID: 874 6940 0953
Passcode: 006683
For the last decade, we have observed an increasing number of companies moving to design their own chips. There is also a never-ending rise in performance requirements to support growing application needs, which leads to higher system complexity and a shorter time to market pressure. The Electronic Design Automation (EDA) tool is one of the key drivers to empower these trending changes and pilot significant growth of the semiconductor market. The EDA market is projected to reach the value of USD 19.60 billion by 2029, at a CAGR of 6.75% during the forecast period. This is era full of Opportunities and Challenges of EDA tool vendors.
Agenda (subject to change):
4:00 – 4: 05 Welcome from CASPA BOD & President
4:00 – 4 : 25 Jimmy chen, Chief of Staff, Synopsys
4:25 – 4: 50 CT Kao, Director of Cadence
4:50 – 5: 15 Norman Change, Fellow, Ansys
5:15 – 6:00 Panel Discussion
Speaker I
Jimmy Cheng, Chief of Staff at Synopsys
Jimmy Cheng is Chief of Staff at Synopsys. In this role, Jimmy is responsible for strengthening and expanding Synopsys’ EDA line of business, including design signoff, physical verification, end-to-end power analysis and optimization, extraction, characterization, memory analysis, 3DIC, design robustness, AI application for chip design software business of Synopsys. Our team is relentlessly innovating across a broad spectrum of EDA technologies to enable semiconductor companies achieve their product ambitions. Prior to Synopsys, Jimmy has held senior management role at Oracle’s SPARC processor design division. Mr. Cheng has over 20 years of industry experience working at Sun Microsystems, NASA’s Jet Propulsion Laboratory. Mr. Cheng holds a Master of Science degree in Electrical Engineering from Stanford University.
Speaker II
CT Kao, Solution Architect, Group Director of Cadence
Speaker III
Norman Chang, Ansys Fellow, IEEE Fellow
Norman Chang is the chief technologist at Semiconductor BU, ANSYS. His research interests include ADAS reliability and ML-based engineering applications. Chang received a PhD in electrical engineering and computer sciences from the University of California, Berkeley. He holds 13 patents and has authored over 50 technical papers.
Moderator
WeiKai Sun, VP of Synopsys
WeiKai Sun has 20 years’ experience of building up flows/methodologies/infrastructures and delivering physical implementation for analog/mixed-signal chips, SoC, microprocessors, and broad spectrum of semiconductor IPs, using various process technologies (from 0.35um HV to 14nm finfet). Built design flow include high level behavioral modeling, front end synthesis and optimization, schematic to layout automation, custom circuit front to back flow, chip level back end extraction and analysis, DFM, semi-custom design flows, and tapeout infrastructure. Built in house Standard Cell libraries, including characterization methodology, various electrical and physical views.
Experience in design, development, and marketing of large-scale software applications/systems, including 3D full chip parasitic extraction, 3D field solver, power and signal integrity solutions. Full project life cycle experience includes product positioning, technical marketing, planning and scheduling, integrating, testing, release, and customer support.
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